1. Field of the Invention
This invention is related to the field of memory systems and, more particularly, to page mode memory systems.
2. Description of the Related Art
Memory systems typically include dynamic random access memory (DRAM) of one type or another. DRAM may include asynchronous DRAM, synchronous (SDRAM), double data rate SDRAM (DDR SDRAM), SyncLink DRAM (SLDRAM), Rambus DRAM (RDRAM), etc. Generally, DRAM memory is an array of storage locations arranged into rows and columns. To access (e.g. read or write) a given storage location in the DRAM, the DRAM receives a row address selecting the row including the storage location and a column address selecting the column including the storage location. Each storage location may be capable of storing one or more bits. The row and column addresses are typically multiplexed onto a set of address lines. Thus, a DRAM storage location may be accessed by transmitting the row address on the address lines and subsequently transmitting the column address on the address lines.
To allow for reduced latency if several storage locations in the same row are accessed consecutively, most DRAMs support a page mode. In page mode, the row address is transmitted to the DRAM, followed by the column address of the first storage location to be accessed. Then, to access additional storage locations in the same row, the column addresses of the additional storage locations may be transmitted without retransmitting the row address. Thus, the additional storage locations may be accessed in less time than the initial storage location, since the row address does not have to be transmitted each time. The storage locations selected by one row address are referred to herein as a xe2x80x9cpagexe2x80x9d. Keeping the page selected, so that only column addresses are used to access other storage locations in the page, is referred to as keeping the page open, and deselecting the row so that a new row address is transmitted to access a storage location is referred to as closing the page. Some DRAMs, such as SDRAMs, include banks of rows and columns. In such DRAMs, the page may be one row within one bank. While a page has been described with respect to DRAMs, a page may refer to storage locations in any memory which selects a storage location for access in response to a row address and a column address.
Operating in page mode is not without penalty, however. Particularly, page mode is maintained by keeping the page within the DRAM selected. In asynchronous DRAMs, the row is selected by activating a row address strobe (RAS) signal and sending the row address on the address lines. In synchronous DRAMs, an activate command is transmitted to the DRAM along with the row address. In response to the row address, the DRAM reads the page into a temporary storage location coupled to the DRAM memory (e.g. the senseamps used to sense the data in the storage locations or some other clocked storage device). The page remains in the temporary storage as long as the page is open (e.g. as long as RAS remains activated, in an asynchronous DRAM, or until a command is sent to close the row, in a synchronous DRAM). Thus, if access to a storage location in a different page is desired, that access is delayed while the previous page is closed (by deasserting RAS or by sending the command to close the row). Time elapsing while the previous page is closed increases the latency of that access, as compared to if the page had been closed at the completion of the previous access.
Typically, memory controllers have been configured to enable or disable page mode, and may have been programmable with various page mode policies. However, the existing mechanisms generally do not allow fine grain control over whether a page corresponding to a given memory access should be kept open or not. Thus, pages may frequently be closed when it would have been advantageous to keep them open and pages may frequently be kept open when it would have been advantageous to close them.
The problems outlined above are in large part solved by a system including an agent and a memory controller as described herein. The agent may initiate transactions targeting a memory to which the memory controller is coupled (e.g. the memory may be some form of DRAM). Memory transactions may include a page hint indication. The page hint indication is transmitted during the transaction by the agent, and may be an indication of whether or not the page addressed by the transaction should be kept open or closed. In other words, the indication may be a hint by the agent regarding the closing or keeping open of the page. An agent may indicate that the page should be kept open if an additional transaction or transactions within the same page of memory are likely (e.g. if the agent itself is going to transmit or may transmit additional transactions within the same page). In such cases, the agent may indicate, via the page hint indication, that the page should be kept open. The additional transactions may experience page mode hit latencies. In other cases, the agent may indicate that the page should be closed. Additional transactions to other pages may not experience the latency required to close the page, if the page is closed in response to the hint. The system may experience reduced overall memory latency due to the more efficient use of page mode.
The memory controller may receive the page hint indication. When accessing the storage location(s) in the memory in response to the memory transaction, the memory controller may close the page or keep the page open responsive to the page hint indication. Thus, fine grain control of which pages are kept open and which pages are closed may be provided. That is, each agent may indicate, on a transaction by transaction basis, whether given pages should be kept open or closed. Since the requesting agent may have some information about whether or not additional transactions are likely to that page and may transmit a page hint indication accordingly, pages may more often be kept open when it would be advantageous to do so, and may more often be closed when it is advantageous to do so.
Broadly speaking, a system is contemplated comprising an agent and a memory controller. The agent is configured to initiate a first transaction and to transmit a page hint indication during the first transaction. The page hint indication is indicative of whether or not a page addressed by the first transaction should be kept open. Coupled to receive the page hint indication, the memory controller is configured to selectively keep the page open in a memory coupled to the memory controller responsive to the page hint indication.
Additionally, an agent is contemplated. The agent comprises a circuit configured to initiate a first transaction and to transmit a page hint indication during the first transaction. The page hint indication is indicative of whether or not a page addressed by the first transaction should be kept open.
Moreover, a memory controller is contemplated, comprising a queue and a circuit coupled thereto. The queue is coupled to receive a first transaction and a page hint indication corresponding to the first transaction. The page hint indication is indicative of whether or not a page addressed by the first transaction should be kept open. The circuit is configured to communicate with a memory addressed by the first transaction, wherein the circuit is configured to selectively keep the page open in the memory responsive to the page hint indication.
Still further, a method is contemplated. A first transaction and a corresponding page hint indication are received. The page hint indication is indicative of whether or not a page addressed by the first transaction should be kept open. The page is selectively kept open responsive to the page hint indication.